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74LS Fairchild Semiconductor, 74LS Datasheet
Most chips come with four AND gates in one, or 6 inverters in one. I figure since the latter was normally used in older computer systems, the power supply and input signals are expected to be well-filtered and free of noise.
When the clock goes to 10, 11, or 12, the “C” is turned off so the digit 1 appears.
I never had a problem with this in my other two clocks that run off mains, and I discovered the reason after taking a closer look at the datasheets. This falling edge triggers the 74LS to advance one more time. This current draw will pull up the clock input of the 74LS to a logic 1 momentarily.
Without the K resistor and 0. I was faced with the problem of the clock starting at 00 hours, but the clock does count nicely to 12 and resets back to I tossed this idea out and decided to drive the nixies directly, using BCD-to-7segment decoder chips.
Therefore, both diodes have to have a logic 1 in order to allow the output to rise to a logic 1. As you can see in the schematic, the portion marked in blue uses two AND gates and one inverter 74,s393.
One advantage to use what is essentially a binary clock with 7-segment decoders is to have small neon bulbs or LEDs driven directly from the BCD outputs. However, that didn’t work out due to complications with the circuitury and the amount of room in the clock case I made. The other segments for the zero are all wired together and switched on and off by a flip-flop. If you used 60Hz from mains and fed it into thethere was still some noise passing through that would dataheet the 74LS’s go haywire.
After discovering this noise problem, I swapped them around. As a result, when the clock is turned on, the 1 is always on. This configuration helped solve the problem. This would’ve been a bad waste of chips, so I decided to do the remaining logics the old school way The datasheet says the chip was designed to have a strong tolerance for noise, and there datasheeg no mention of this in the 74LS datasheet. Recall that the 74LSs trigger on a falling edge, not a rising edge.
So, when the hours runs to 13, the AND gate will reset the hours to zero, then the DRL will produce a logic 1 because it senses 00 hours. I think if the 74LS operated on a rising edge, the circuit might work without the capacitor and resistor.
Assembly and Testing Completed view datashheet assembly bottom view Back to Top. A colon indicator can be added by using the 1Hz pulse off pin 5 of U3a.
I had to use a very small 8-volt transformer that just barely fits inside the case to supply the low voltage power. I originally planned on using a Mostek MK 6-digit clock chip that multiplexes the digits. Below is the pinout of the B nixie: The pulse goes high then low, and the falling edge triggers the 74LS After overcoming the noise problem with the 74LSs in the clock, I learned of another minor design issue.
I experimented with using 74LS dual binary counter chips. The and triggers on the rising-edge. It took some experimentation before I could get the signals to work correctly between the chips. Then the DRL output goes high 47ls393 the capacitor starts to charge up.
However, I had to delay the pulse from the DRL until the 10 minutes counter finished sending its clock pulse to the 1 hours counter. In the process of constructing the clock, I found that these chips were extremely sensitive to noise.
74LS Datasheet(PDF) – TI store
These versatile nixie tubes can allow for a variety of characters and digits with different styles. I personally prefer hour mode.
The fundamentals of my binary clock circuitry was based on Hans Summer’s binary clock, but his operates in hour mode. I figured that if the clock was going to roll over to 00 hours, I’d need a “double” pulse to get the hours to automatically advance to 01 hours. The inverter using a transistor and resistor changes the “off” G into a logic 1 for the AND gate. For the ten hours, I didn’t want to waste another 74LS and chip just to display zero and one.
I planned on placing the neon bulbs under each digit, so if you’re plain then look at the Bs and if you’re a geek then look at the binary below. However, after trying the chip out with two nixies, I found that the brightness was not very strong.
I came to a point where I thought I had gotten the design, so I proceed to build the clock. None of the other digits have this trait.
For this clock, I decided to go with the traditional 7-segment display to show the time. I designed the clock circuitury hoping datasjeet achieve a perfect design that uses all of the logic available in all of the chips I would need. Click here for the schematic diagram of the four B nixie clock. I used the for the first stage to divide 60Hz to 10Hz. Anyway, on to the pictures. The “C” that is switched on to make a zero comes on when the clock is in the single digit hours.
I also found out that the circuitry draws a good amount of current so I couldn’t simply obtain low voltage from the voltage doubler and regulate it for the low voltage supply like I could in my first two nixie clocks.
The 74LS clock input triggers on a falling-edge of a square wave when the square wave signal drops from a logic 1 to 0. Even a seconds display can be added to this circuit, simply add two more decoder chips on U3b and U4a. I built a case out of cedar, and the amount of space I had inside the case was rather limited so I was unable to pursue my idea of using neon bulbs or LEDs for displaying the binary time directly from the 74LS counters.
I realized a design flaw when I finished the clock.